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The bottom of deep submicron

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The impact of scaling down to deep submicron on CMOS RF circuits

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To browse Academia. Skip to main content. Log In Sign Up. Download Free PDF. Paolo Orsatti. Download PDF. A short summary of this paper.
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EP0600814B1 - Transistor with deep submicron channel - Google Patents

The use enters a set of fairly fundamental properties of the technology such as interconnect layer thickness, and logic depth and the program estimates the system level performance of an IC built with these assumptions. Previous work in this area can be found in [1] and, [2] but these do not consider many of the effects of deep-sub-micrometre interconnect. BACPAC uses analytical approximations for system properties such as delay and interconnect requirements.
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The effects of cleaning and treatment on the characteristics of contact-hole-bottom Si surfaces are investigated in order to reveal the origin of the increased contact resistance and to find treatment processes that can be used to obtain low contact resistance. Contact-hole-bottom Si surfaces were analyzed by using thermal desorption spectroscopy, transmission electron microscope, and energy-dispersive x-ray spectroscopy. Nonpatterned Si surfaces, which roughly simulate the properties of the contact-hole-bottom Si surfaces, were also analyzed by using x-ray photoelectron spectroscopy. It is revealed that suboxide-rich native oxide layers are formed on dry-etch-damaged Si surfaces.
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